In current data centers, the use of multi-processor servers is very popular. Each server typically includes a circuit board having a number of sockets configured to fit various components, including multiple processors or CPUs, an interface for performing external communication, and various other components. Some of these may be incorporated into the circuit board or may fit into dedicated socket(s) on the circuit board. The CPUs include connectors having a form factor that mates with CPU sockets on the circuit board. Stated differently, the CPU sockets on the circuit board have the same form factor as the connectors (or pins) for the CPU. In operation, each server board performs calculations using at least its internal CPUs.
In recent server architectures, each CPU/socket on the circuit board is coupled to a dedicated memory, such as a dual in-line memory module (DIMM), to provide faster access to items in the dedicated memory. Consequently, the DIMM for the first CPU is usable only by the first CPU and the DIMM for the second CPUs usable only by the second CPU.
One problem with multiple processor servers is that some server applications may not require use of multiple CPUs. If a single CPU is adequate for the computational needs, a second socket in the circuit board may be left empty. Use of a single CPU in the server board may reduce the power consumption, which is generally desirable. There is also a cost savings due to the omission of the second CPU. However, because each CPU socket and thus each CPU typically has dedicated memory, leaving one of the CPU sockets empty may preclude access to the dedicated memory assigned to the empty CPU socket and a portion of the total memory capacity of the server may be lost. Thus, the reduction in power and cost achieved by omitting a CPU may be offset by limitations in the memory for the server board for many applications which require large memories but are not calculation intensive.
Accordingly, it would be desirable to accommodate omitting one or more CPUs from a multi-I processor server board, while maintaining accessibility to the dedicated memory assigned to the empty CPU sockets.